#ifndef __CANDEF_H
#define __CANDEF_H

/**************************************************************************
 ---- Baud-rate calculations ----

 Fosc		= 16MHz
 BRP			= 7
 TQ 			= 2 * (BRP + 1) / Fosc
 = 1 uS

 Sync Seg	= 					= 1 TQ
 Prop Seg	= (PRSEG + 1) * TQ			= 1 TQ
 Phase Seg1	= (PHSEG1 + 1) * TQ			= 3 TQ
 Phase Seg2	= (PHSEG2 + 1) * TQ 			= 3 TQ
 --------
 8 TQ

 Bus speed	= 1 / ((Total # of TQ) * TQ)
 = 1 / (8 * TQ) = 125 kHz

 **************************************************************************/

// Define Can MCP2515 register addresses

#define RXF0SIDH	0x00
#define RXF0SIDL	0x01
#define RXF0EID8	0x02
#define RXF0EID0	0x03
#define RXF1SIDH	0x04
#define RXF1SIDL	0x05
#define RXF1EID8	0x06
#define RXF1EID0	0x07
#define RXF2SIDH	0x08
#define RXF2SIDL	0x09
#define RXF2EID8	0x0A
#define RXF2EID0	0x0B
#define BFPCTRL		0x0C
#define TXRTSCTRL	0x0D
#define CANSTAT		0x0E
#define CANCTRL		0x0F

#define RXF3SIDH	0x10
#define RXF3SIDL	0x11
#define RXF3EID8	0x12
#define RXF3EID0	0x13
#define RXF4SIDH	0x14
#define RXF4SIDL	0x15
#define RXF4EID8	0x16
#define RXF4EID0	0x17
#define RXF5SIDH	0x18
#define RXF5SIDL	0x19
#define RXF5EID8	0x1A
#define RXF5EID0	0x1B
#define TEC		0x1C
#define REC         	0x1D
#define CANSTAT1	0x1E
#define CANCTRL1	0x1F

#define RXM0SIDH	0x20
#define RXM0SIDL	0x21
#define RXM0EID8	0x22
#define RXM0EID0	0x23
#define RXM1SIDH	0x24
#define RXM1SIDL	0x25
#define RXM1EID8	0x26
#define RXM1EID0	0x27
#define CNF3		0x28
#define CNF2		0x29
#define CNF1		0x2A
#define CANINTE		0x2B
#define CANINTF		0x2C
#define EFLG		0x2D
#define CANSTAT2	0x2E
#define CANCTRL2	0x2F

#define TXB0CTRL	0x30
#define TXB0SIDH	0x31
#define TXB0SIDL	0x32
#define TXB0EID8	0x33
#define TXB0EID0	0x34
#define TXB0DLC		0x35
#define TXB0D0		0x36
#define TXB0D1		0x37
#define TXB0D2		0x38
#define TXB0D3		0x39
#define TXB0D4		0x3A
#define TXB0D5		0x3B
#define TXB0D6		0x3C
#define TXB0D7		0x3D
#define CANSTAT3	0x3E
#define CANCTRL3	0x3F

#define TXB1CTRL	0x40
#define TXB1SIDH	0x41
#define TXB1SIDL	0x42
#define TXB1EID8	0x43
#define TXB1EID0	0x44
#define TXB1DLC		0x45
#define TXB1D0		0x46
#define TXB1D1		0x47
#define TXB1D2		0x48
#define TXB1D3		0x49
#define TXB1D4		0x4A
#define TXB1D5		0x4B
#define TXB1D6		0x4C
#define TXB1D7		0x4D
#define CANSTAT4	0x4E
#define CANCTRL4	0x4F

#define TXB2CTRL	0x50
#define TXB2SIDH	0x51
#define TXB2SIDL	0x52
#define TXB2EID8	0x53
#define TXB2EID0	0x54
#define TXB2DLC		0x55
#define TXB2D0		0x56
#define TXB2D1		0x57
#define TXB2D2		0x58
#define TXB2D3		0x59
#define TXB2D4		0x5A
#define TXB2D5		0x5B
#define TXB2D6		0x5C
#define TXB2D7		0x5D
#define CANSTAT5	0x5E
#define CANCTRL5	0x5F

#define RXB0CTRL	0x60
#define RXB0SIDH	0x61
#define RXB0SIDL	0x62
#define RXB0EID8	0x63
#define RXB0EID0	0x64
#define RXB0DLC		0x65
#define RXB0D0		0x66
#define RXB0D1		0x67
#define RXB0D2		0x68
#define RXB0D3		0x69
#define RXB0D4		0x6A
#define RXB0D5		0x6B
#define RXB0D6		0x6C
#define RXB0D7		0x6D
#define CANSTAT6	0x6E
#define CANCTRL6	0x6F

#define RXB1CTRL	0x70
#define RXB1SIDH	0x71
#define RXB1SIDL	0x72
#define RXB1EID8	0x73
#define RXB1EID0	0x74
#define RXB1DLC		0x75
#define RXB1D0		0x76
#define RXB1D1		0x77
#define RXB1D2		0x78
#define RXB1D3		0x79
#define RXB1D4		0x7A
#define RXB1D5		0x7B
#define RXB1D6		0x7C
#define RXB1D7		0x7D
#define CANSTAT7	0x7E
#define CANCTRL7	0x7F

#define MCP_TX_INT		0x1C		// Enable all transmit interrupts
#define MCP_TX01_INT	0x0C	// Enable TXB0 and TXB1 interrupts
#define MCP_RX_INT		0x03		// Enable receive interrupts
#define MCP_NO_INT		0x00		// Disable all interrupts
#define MCP_TX01_MASK	0x14
#define MCP_TX_MASK		0x54

// CANCTRL Register Values

#define MODE_NORMAL     0x00
#define MODE_SLEEP      0x20
#define MODE_LOOPBACK   0x40
#define MODE_LISTENONLY 0x60
#define MODE_CONFIG     0x80
#define MODE_POWERUP	0xE0
#define MODE_MASK		0xE0
#define ABORT_TX        0x10
#define MODE_ONESHOT	0x08
#define CLKOUT_ENABLE	0x04
#define CLKOUT_DISABLE	0x00
#define CLKOUT_PS1		0x00
#define CLKOUT_PS2		0x01
#define CLKOUT_PS4		0x02
#define CLKOUT_PS8		0x03

// CNF1 Register Values

#define SJW1            0x00
#define SJW2            0x40
#define SJW3            0x80
#define SJW4            0xC0

// CNF2 Register Values

#define BTLMODE		0x80
#define SAMPLE_1X       0x00
#define SAMPLE_3X       0x40

// CNF3 Register Values

#define SOF_ENABLE	0x80
#define SOF_DISABLE	0x00
#define WAKFIL_ENABLE	0x40
#define WAKFIL_DISABLE	0x00

// CANINTF Register Bits
#define CANINTF_RX0IF	0x01
#define CANINTF_RX1IF	0x02
#define CANINTF_TX0IF	0x04
#define CANINTF_TX1IF	0x08
#define CANINTF_TX2IF	0x10
#define CANINTF_ERRIF	0x20
#define CANINTF_WAKIF	0x40
#define CANINTF_MERRF	0x80

// CANINTE Register Bits
#define CANINTE_RX0IE	0x01
#define CANINTE_RX1IE	0x02
#define CANINTE_TX0IE	0x04
#define CANINTE_TX1IE	0x08
#define CANINTE_TX2IE	0x10
#define CANINTE_ERRIE	0x20
#define CANINTE_WAKIE	0x40
#define CANINTE_MERRE	0x80

#define BFPCTRL_B0BFM	0x01
#define BFPCTRL_B1BFM	0x02
#define BFPCTRL_B0BFE	0x04
#define BFPCTRL_B1BFE	0x08
#define BFPCTRL_B0BFS	0x10
#define BFPCTRL_B1BFS	0x20

#define TXRTSCTRL_B0RTSM	0x01
#define TXRTSCTRL_B1RTSM	0x02
#define TXRTSCTRL_B2RTSM	0x04

// EFLG Bits

#define RX1OVR 	0x80
#define RX0OVR 	0x40
#define TXB0 	0x20
#define	TXEP	0x10
#define RXEP	0x08
#define TXWAR	0x04
#define RXWAR	0x02
#define EWARN	0x01

// Can MCP2515 settings
#define fosc   16              // MCP2515 horloge
#define tsync  1
#define tprop  3
#define tps1   3
#define tps2   3
#define tot_tq tsync+tprop+tps1+tps2
#define t1M    1
#define t500k  2
#define t250k  4
#define t125k  8
#define t50k   20
#define t20k   50
#define t10k   100
#define b1M    fosc*t1M/2/tot_tq
#define b500k  fosc*t500k/2/tot_tq
#define b250k  fosc*t250k/2/tot_tq
#define b125k  fosc*t125k/2/tot_tq
#define b50k   fosc*t50k/2/tot_tq
#define b20k   fosc*t20k/2/tot_tq
#define b10k   fosc*t10k/2/tot_tq

// Extended identifier
#define EXIDE	3

// MCP2515 CAN SPI Instructions
#define CAN_SPI_READ_RXB0SIDH	0x90	// CAN SPI READ RX BUFFER instruction RXB0 at RXB0SIDH
#define CAN_SPI_READ_RXB0D0		0x92	// CAN SPI READ RX BUFFER instruction RXB0 at RXB0D0
#define	CAN_SPI_READ_RXB1SIDH	0x94	// CAN SPI READ RX BUFFER instruction RXB1 at RXB1SIDH
#define CAN_SPI_READ_RXB1D0		0x96	// CAN SPI READ RX BUFFER instruction RXB1 at RXB1D0
#define CAN_SPI_LOAD_TXB0SIDH	0x40 	// CAN SPI LOAD TX BUFFER instruction TXB0SIDH
#define CAN_SPI_LOAD_TXB0D0		0x41 	// CAN SPI LOAD TX BUFFER instruction TXB0D0
#define CAN_SPI_LOAD_TXB1SIDH	0x42 	// CAN SPI LOAD TX BUFFER instruction TXB1SIDH
#define CAN_SPI_LOAD_TXB1D0		0x43 	// CAN SPI LOAD TX BUFFER instruction TXB1D0
#define CAN_SPI_LOAD_TXB2SIDH	0x44 	// CAN SPI LOAD TX BUFFER instruction TXB2SIDH
#define CAN_SPI_LOAD_TXB2D0		0x45 	// CAN SPI LOAD TX BUFFER instruction TXB2D0
#define CAN_RTS_TXB0 			0x81 	// CAN SPI RTS TXB0 instruction
#define CAN_RTS_TXB1 			0x82 	// CAN SPI RTS TXB1 instruction
#define CAN_RTS_TXB2 			0x84 	// CAN SPI RTS TXB2 instruction
#define CAN_SPI_RX_STATUS		0xB0 	// CAN SPI read RX status
#define CAN_SPI_READ  			0x03	// CAN SPI interface READ instruction
#define CAN_SPI_WRITE	  		0x02	// CAN SPI WRITE instruction
#define CAN_SPI_RESET			0xC0	// CAN SPI RESET instruction
#define CAN_SPI_READ_STATUS		0xA0	// CAN SPI READ Status instruction
#define CAN_SPI_BIT_MODIFY		0x05	// CAN SPI BIT MODIFIY instruction
#endif
